1st practical - cpe104p

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Across
  1. 2. Address range of UROM.
  2. 6. It enables transfers from the monitor ROM.
  3. 7. From figure 3-8, what pin should be activated to select this RAM?
  4. 9. A pin that both RAM and ROM have that enables the transfer of its data to the bus.
  5. 17. It tells the CPU what type of operation to perform.
  6. 18. It is the full scale output voltage divided by the number of input bits.
  7. 19. If RAMSEL is active, what would be the logic level of A17 and A18 based on Figure 3-41?
  8. 23. What is the logic level of W/R# and D/C# if the ROM transfer is a memory code read cycles?
  9. 24. Based on Figure 3-39, what is the CPU doing for the first interval?
  10. 26. If A17 is one and A18 is zero, what memory block is selected?
  11. 27. Register used for the IN and OUT instruction.
  12. 28. If MROMSEL is active, what would be the logic level of A17 and A18 based on Figure 3-41?
  13. 30. Based on Figure 3-8, what would be the operation of the RAM if WE is high.
  14. 31. A mode in ADC that has an input range of -5V to +5V.
  15. 32. lf the CPU samples 8516# low during T2, it sets the bus size to _______ .
  16. 33. What is the first address digit for RAM transfer?
  17. 34. If A17 is zero and A18 is one, what memory block is selected?
  18. 37. It activates when the CPU writes to memory.
  19. 39. Undecoded address lines in the memory space, creates a/an ________.
Down
  1. 1. It is a free-running clock signal of approximately 260KHz.
  2. 3. What is the logic level of M/IO# if the ROM transfer is a memory code read cycles?
  3. 4. A type of memory that contains 16-bit devices.
  4. 5. It enables transfers from user ROM.
  5. 8. It is a process that enables the user to input and output information to and from the CPU.
  6. 10. It a port that connects to JP6 and is used as an 8-bit parallel port.
  7. 11. It is used to communicate with external devices.
  8. 12. It converts an analog signal to a digital signal.
  9. 13. It is a port used for control (handshaking) signals.
  10. 14. Based on Figure 3-39, what is the CPU doing for the fourth interval?
  11. 15. It is used to select a certain block of memory, while the lower CPU address lines specify an exact location within the selected block.
  12. 16. It is necessary to establish the proper timing and logic for efficient memory transfers.
  13. 20. Based on Figure 3-8, how many memory locations?
  14. 21. Address range of RAM.
  15. 22. It activates when the CPU reads from the memory.
  16. 25. Address lines that is decoded to determine the memory block select signals.
  17. 29. It takes a binary input and converts it to an analog voltage.
  18. 35. It enables transfers to and from RAM.
  19. 36. It is used to interface external devices to the CPU.
  20. 38. Which CM switch is turned-ON to insert a switch in the circuit board?