Moulde 1 Processor Architecture

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Across
  1. 4. addressing mode in which address of the memory location is given explicitly
  2. 5. first stage of instruction execution
  3. 6. Three types of bus are Data, control and ________
  4. 7. Brain of the computer
  5. 9. Process by which the next device to become the bus master is selected
Down
  1. 1. Addressing mode suitable for arrays and lists
  2. 2. Chips with 4 cores
  3. 3. Representation where lower byte addresses are used for the MSBs
  4. 8. L1 cache is also referred as _______ cache
  5. 10. condition where result of computation falls outside the representable range