3.1 Latches and Flip Flops

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Across
  1. 2. Counter in which all of the flip-flops are clocked simultaneously.
  2. 4. Type of flip-flop in which inputs J and K are the synchronous inputs.
  3. 6. Digital signal in the form of a rectangular pulse train or a square wave.
  4. 8. The number of cycles per unit time of a periodic waveform.
  5. 9. Flip-flop inputs that can affect the operation of the flip-flop independent of the synchronous and clock inputs.
  6. 11. Type of flip-flop in which the D (data) input is the synchronous input.
  7. 12. The part of a pulse where the logic level is in transition from a HIGH to a LOW.
  8. 13. Delay from the time a signal is applied to the time when the output makes its change.
  9. 18. Asynchronous input used to set Q=0 immediately.
  10. 19. Input signal to a flip-flop or one-shot that causes the output to change states depending on the conditions of the control signals.
  11. 20. Manner in which a flip-flop is activated by a signal transition. A flip-flop may be either a positive- or a negative-edge-triggered flip-flop.
  12. 22. Enabled by a logic HIGH or LOW level.
Down
  1. 1. Type of counter in which each flip-flop output serves as the clock input signal for the next flip-flop in the chain.
  2. 3. A sequential circuit based on a latch whose output changes when its CLOCK input receives a pulse.
  3. 5. Asynchronous input used to set Q=1 immediately.
  4. 7. Fraction of the total period that a digital waveform is in the HIGH state. DC = th/T (often expressed as a percentage: %DC = th/Tx100%).
  5. 10. Digital circuit that accepts binary data from some input source and then shifts these data through a chain of flip-flops one bit at a time.
  6. 14. Digital circuitry in which the output state of the circuit depends not only on the states of the inputs, but also on the sequence in which they reached their present states.
  7. 15. A sequential circuit that advances through several defined states.
  8. 16. The part of a pulse where the logic level is in transition from a LOW to a HIGH.
  9. 17. The amount of time required for one complete cycle of a periodic event or waveform.
  10. 21. Circuit that contains a NAND gate latch and two steering NAND gates.