CMOS Process Technology

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Across
  1. 3. N well is formed by
  2. 5. color is used for polysilicon
  3. 6. few parts of photoresist layer is removed by using _________solution
  4. 9. Silicon oxide is patterned on a substrate using ____________
  5. 10. gate is to transfer strong 0 and 1
  6. 12. based layout design rules
  7. 14. region exists when gate source voltage is zero in nmos.
Down
  1. 1. inverter has no static power dissipation
  2. 2. is indicated by crossing diffusion with polysilicon in stick diagram
  3. 4. design includes the design of transistors
  4. 7. design involves planning placement and routing
  5. 8. voltage between the gate and the source terminals below which the drain to source current effectively drops to zero.
  6. 11. diagrams are those which convey layer information through?
  7. 13. is used to identify the place in which Ion Implantation should not be occurred.