Computer Architecture

123456789
Across
  1. 2. addressing mode suitable for arrays and lists
  2. 3. Brain of the computer
  3. 7. Process by which the next device to become the bus master is selected
  4. 8. Three types of bus are Data, control and ________
  5. 9. chips with 4 cores
Down
  1. 1. representation where lower byte addresses are used for the more significant bytes
  2. 4. L1 cache is also referred as _______ cache
  3. 5. first stage of instruction execution
  4. 6. result of computation falls outside the representable range
  5. 7. addressing mode in which address of the memory location is given explicitly in the instruction