COMPUTER ORGANIZATION

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Across
  1. 4. Common interrupt request line is implemented using(10)
  2. 7. DMA controller may be given exclusive access to main memory to transfer block of data without interruption(9)
  3. 8. Serial connection of all devices that request an interrupt(10)
  4. 11. Unexpected process within processor(9)
  5. 12. Request for keyboard enable(4)
  6. 13. simple arrangement to connect I/O device to computer(9)
Down
  1. 1. Set of rules that govern the behavior of various device connected to bus(11)
  2. 2. Delay between IR received and starting execution of ISR(16)
  3. 3. The clockpulse width t1 to t0 must be longer than ____ in synchronous bus(16)
  4. 5. procedure in which a dispute is submitted by agreement of parties(11)
  5. 6. channel for number of bytes transferred during DMA transfer(9)
  6. 8. Process of eliminating errors(9)
  7. 9. A unit which performs specific task performed by calling function(10)
  8. 10. In program controlled I/O processor repeteadly checks____(10)