ECE2072

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Across
  1. 2. Most digital applications
  2. 7. Perform logical computations
  3. 12. Clock unsynced
  4. 14. Real-life problems
  5. 16. Software
  6. 18. Temporary variable in Verilog
  7. 21. A block in Verilog
  8. 22. Reduction method
  9. 24. Hardware Description Language
  10. 25. Two digits only
  11. 26. Easy to modify in Verilog
  12. 28. A type of map
  13. 29. Edge-triggered
Down
  1. 1. State output
  2. 3. A bus of bits
  3. 4. State reduction
  4. 5. Negative
  5. 6. No other way
  6. 8. All possible combinations
  7. 9. One become many
  8. 10. Term reduction
  9. 11. Glitch
  10. 13. Dynamic & timing analysis
  11. 15. Sequence independent
  12. 17. Design type
  13. 19. Name of theorems
  14. 20. Discreet values
  15. 23. Level-triggered
  16. 27. Many into one
  17. 30. Minterm or maxterm