RTL DESIGN WITH VERILOG/VHDL HDL

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Across
  1. 2. Which design involves floor planning of design?
  2. 5. Performs sum of two binary operands.
  3. 8. Which assignment is used to describe sequential logic?
  4. 9. Next step of functional requirement of the design.
  5. 11. The port which is used in verilog to declare input?
  6. 12. {} denotes..
  7. 13. Different from software language which is useful in hardware.
Down
  1. 1. Which assignment is used to describe combinational logic?
  2. 3. In verilog hdl /* …… */ indicates ?
  3. 4. Which use two single or multiple-bit operands?
  4. 6. {m,{}} denotes..
  5. 7. Verilog starts with?
  6. 10. Which operator is used to invert the binary operands?