Quiz-5: Computer Architecture: Caches

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Across
  1. 3. Caches are designed using this memory technology
  2. 6. A common coherence protocol
  3. 10. Exploit spatial locality beyond block size
  4. 13. In a multi-level cache system, the cache just before memory
  5. 14. A write operation can set this bit
  6. 16. The kind of miss not seen by a fully associative cache
  7. 20. Used to reduce miss penalty due to dirty block eviction
Down
  1. 1. A low-overhead alternative to cache
  2. 2. Cache where instruction and data can be stored together
  3. 4. The number of eligible cache locations for a given block
  4. 5. When one block can go to only a fixed location
  5. 7. Number of tag bits in 16KB, fully-associative, 128 Byte block cache with 30-bit address
  6. 8. When the cache and memory are updated together
  7. 9. Type of locality in k++
  8. 11. Number of offset bits in 8KB, 2-way, 256 Byte block cache
  9. 12. The B in ABC of caches
  10. 15. Memory organization with tradeoff in bus width and access time
  11. 17. Number of index bits in 32KB, 4-way, 64 Byte block cache
  12. 18. A replacement policy unfair to recently fetched block
  13. 19. The block that gets replaced