Across
- 2. A computer architecture that has two separate areas of memory - one for instructions & one for data. Instructions and data can be accessed concurrently. Different sets of buses - one for instructions & one for data.
- 4. Is slower than the L1 cache but bigger in size, between 256KB and 8MB.
- 7. Shared between the cores in a CPU, it is the largest but slowest cache memory often between 8 and 64MB in size.
- 10. A CPU design that produces a complicated and expensive integrated circuit capable of performing a large variety of complex instructions. Complex instructions can be executed with few machine cycles.
- 11. Any modern set of disciplines that describes the functionality, the organisation and the implementation of computer systems.
- 13. A special purpose CPU designed to handle high volumes of small calculations, often use with graphical processing. These of formed of many cores to perform many operations in parallel.
- 14. Usually part of the CPU chip itself and is both the smallest and the fastest to access. Its size is often restricted to between 8 KB and 64 KB.
- 15. A computer architecture that has data and Instructions stored in the same format in the same RAM. Single set of buses for fetching data and instructions.
Down
- 1. A part of the main store between the CPU and the rest of the memory. It has extremely fast access
- 3. A CPU design that produces a simple, cheap integrated circuit with a basic range of machine instructions. Relies on speed as complex instructions take many machine cycles.
- 5. A complete processing unit within the CPU that has its own ALU, CU and registers. There can be more than one of these inside a CPU
- 6. A CPU consisting of two or more cores, each core can can execute multiple instructions in parallel.
- 8. Measured in hertz or cycles per second, it represents how many instructions per second the processor can execute.
- 9. A method in computing of running two or more processors (CPUs) to handle separate parts of an overall task.
- 12. The process of fetching an instruction whilst decoding another and executing another in order to increase the capacity of the processor.
