Масальцов

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Across
  1. 2. Logic deciding which runnable entity obtains CPU time next.
  2. 5. Central component handling scheduling memory management device control and system calls.
  3. 6. Movement of memory pages between secondary storage and main memory under memory pressure.
  4. 8. Techniques coordinating concurrent access to shared resources preventing races and inconsistency.
  5. 12. Student's surname author of the work.
  6. 13. Address translation and paging mechanism decoupling logical addresses from physical frames.
Down
  1. 1. Temporary storage area smoothing speed differences between producer and consumer of data.
  2. 3. Core software layer that manages hardware resources and offers standardized services to applications.
  3. 4. Structures and rules organizing naming allocation and metadata of persistent data.
  4. 7. Lightweight execution context sharing memory and open resources within a process.
  5. 9. Asynchronous signal diverting normal execution flow to a handler for timely event processing.
  6. 10. Isolated running instance of a program with its own address space and resource descriptors.
  7. 11. Module providing standardized interface between the OS and a specific hardware device.