21EC71 Activity-1 Quiz

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Across
  1. 3. A _________ seed is fixed and not allowed to move during the remaining floorplanning and placement steps.
  2. 5. ____________ phase, which assign a specific location to blocks.
  3. 6. In a _______ adder we duplicate two small adders for the cases CIN = '0' and CIN = '1' and then use a MUX to select the case that we need.
  4. 11. In FPGA, none of the ________ layers are customized.
  5. 13. In the ASIC design flow, ______ determine the resistance and capacitance of the interconnect.
  6. 15. The ASIC designer defines only the placement of the standard cells and the interconnect in a _____
  7. 17. In physical design flow, From the initial floorplan __________ capacitances are input to the synthesis tool as load constraints and intrablock capacitances are input as wire-load tables.
  8. 19. A __________ placement method uses a set of rules to arrive at a constructed placement.
  9. 20. sometimes the I/O power is known as ________ power since it has to supply large transient currents to the output transistors.
Down
  1. 1. One of the objectives of global routing is to ___________ the critical path delay.
  2. 2. In _________ gate array, there are no predefined areas set aside for routing - routing is over the top of the gate-array devices.
  3. 4. _______ routing first partitions the routing region into tiles and decides tile-to-tile paths for all nets while attempting to optimize some given objective function.
  4. 7. One measure of the _________ is the difference between the number of interconnects that we actually need, called the channel density , and the channel capacity.
  5. 8. ____________ phase, which consists of planning and sizing of blocks and interconnect.
  6. 9. In _________ model represents ESD by a 100 pF capacitor discharging through a 1.5 k W resistor.
  7. 10. Automated layout assembly tools, often known as a _______ compilers.
  8. 12. The difference between the required and arrival times at each input pin is the _____ time.
  9. 14. A design in which the core area dominates over the area taken by the I/O pads (including pads related to power) is known as a _____ limited design.
  10. 16. An EPROM content can be erased by exposing it to _______ light rays.
  11. 18. In channel gate array, only the ___________ is customized.