Computer Architecture

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Across
  1. 3. Processor Performance
  2. 7. Highest Priority in LRU Policy
  3. 8. Number of prefetch requests to issue at a given time
  4. 10. Prefetcher with degree = 1 and distance = 1
  5. 12. Misses that would occur even under optimal replacement policy
  6. 14. Measure of cache Performance
  7. 15. Volatile random access memory
  8. 16. Byte ordering within a word
  9. 18. Four states of a cache block
  10. 19. Reuse of specific data/resources within a relatively small time duration
  11. 21. Cache for evicted data
Down
  1. 1. Stored program concept
  2. 2. Write only into the cache block on hit
  3. 4. One virtual page maps to two physical pages
  4. 5. Whole set of data an executing application references within a time interval
  5. 6. Executing multiple instructions in parallel
  6. 9. CISC with RISC misteries
  7. 11. Released first commercial Dram
  8. 13. Speedup
  9. 17. First reference misses
  10. 20. ISA with small semantic gap