Design For Test

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Across
  1. 2. additional control or observe point to increase scannability of a design
  2. 5. complex logic that generates or modifies clock signals internal to the product
  3. 8. file that can be used for analyzing power during scan test
  4. 10. memories are usually treated like this during scan
  5. 12. memory fault wherein the value of a cell is influenced by an operation/content of another cell
  6. 13. node of a flop that is not covered by the most simple scan architecture
  7. 17. one consideration for PMBIST grouping of memories
  8. 18. feature of some memories to fix faults through spare or redundant columns/rows
  9. 21. design for test
  10. 23. test controller unit in a PMBIST system
  11. 25. cadence tool for scan analysis and test pattern generation
  12. 26. spyglass task that checks for scannability of a design
  13. 28. allows for testing faults in a memory
  14. 30. what Q in IDDQ stands for
  15. 31. file from synthesis that contains the scan pins information
  16. 33. storage element/cell that can cause coverage loss
  17. 34. tool for insertion and verification of MBIST
  18. 35. IEEE standard for verifying and testing designs after manufacture
  19. 36. registers of the design connected in a shift register fashion
  20. 38. number of stuck-at faults in a half-adder cell
Down
  1. 1. scan coverage requirement for non-automotive products
  2. 3. built in testing of logic circuits
  3. 4. one of the mandatory instructions for boundary scan and is a non-invasive operational mode
  4. 6. optional atpg step to reduce test patterns through reordering tests
  5. 7. technique to block X values from propagating through the scan logic
  6. 9. most important metric of scan
  7. 11. fault model used for static scan
  8. 12. scan technique to reduce the number of vectors through splitting the internal scan chains
  9. 14. file that contains testmode initialization sequence
  10. 15. pattern conversion tool
  11. 16. what P in PMBIST stands for
  12. 19. data and ____ : two variables that are important in determining a PMBIST algorithm
  13. 20. adflow task for scan pattern generation
  14. 22. also called delay fault
  15. 24. a memory type
  16. 27. scan that is used to control and observe the functional ports of a chip
  17. 29. adflow task where scan chains are created
  18. 32. retention tests are created for these kinds of cells
  19. 34. equipment that executes the scan tests
  20. 37. data format used by Cadence for scan failures diagnostics