DIGIETRONIX-2025- C

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Across
  1. 2. The number of half adders needed to implement a full adder is __
  2. 4. The min number of 2 input NAND gates needed to implement a 2 input exor function is___
  3. 5. In a __ adder made using 4bit binary adders,the correction factor is 0110
  4. 6. IC 7410 has ___ gates within it
  5. 7. Min time that an i/p signal must be constant, after a clock trigger,to reliably operate a F/F is
  6. 9. The carry propagate function in CLA is ___
  7. 10. The PI terms which are mandatorily included in minimal SOP expression
  8. 12. This module produces N outputs from m inputs with N = 2 power m
  9. 13. The highest modulus of counter that can be implemented using 7492 is __
  10. 15. A combination block which is used a universal element in FPGA designs is
  11. 17. IC 7402 has ____ gates inside
  12. 18. ___is a problem associated with asynchronous counters
  13. 19. In a T flip flop with T=0, when clocked the output is( one,zero,toggles,nochange,past)
Down
  1. 1. In QM approach, the no of 1's in a binary representation of a number is called _____
  2. 2. Fan-in of 7411 is
  3. 3. The hamming distance between 2 codewords in grey code is
  4. 4. AND gates and ______ are needed to implement a combinational binary multiplier
  5. 6. A (7,4) hamming code needs minimum ___ parity bits
  6. 8. CLA is much faster than RCA as length of data increases(yes/no)
  7. 9. The johnson counter with 4 flipflops will have ____ modulus
  8. 11. stands for (min,max)terms - Choose the right answer
  9. 12. __ circuit takes input on a single line and transmits this onto 2 power n possible output lines
  10. 14. ___is a problem with synchronous counters
  11. 16. A boolean function of 3 variables can be mapped to a K map of size