dynamic CMOS logic

Edit Answers
1234567
Across
  1. 1. ____-nMOS has higher pull-up resistance than nMOS device and thus inverter pair delay is larger
  2. 5. CMOS domino logic has smaller parasitic______ and higher operating speed
  3. 7. phase clock is used in dynamic CMOS logic
Down
  1. 2. in CMOS circuits, which type of power dissipation occurs due to switching of transient current and charging & discharging of load capacitance?
  2. 3. CMOS domino logic is same as that of the ____CMOS logic with inverter at the output line.
  3. 4. in pseudo-nMOS logician transistor operates in___ region
  4. 6. domino logic, single phase clock is use