ICDET - 3a

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Across
  1. 1. Condition for NMOS inverter is that R2 much ____ than R1
  2. 2. Electron ____ is about twice that of hole’s
  3. 3. For NMOS inverters, output voltage can never reach a ____ 0V
  4. 6. After calculating Ids1 and Ids2, next is to put Ids1 ___ to Ids2
  5. 7. One of the advantages of CMOS inverters
  6. 9. Delays will affect the operating ____ of a digital circuit
  7. 10. L/W is known as the ___ ratio Z, of a transistor
  8. 12. Zpu/Zpd is known as the ___ ratio
Down
  1. 1. ___ are used to select or control the flow of signals
  2. 4. How fast a signal can go from ‘1’ to ‘0’ is known as ___ time
  3. 5. For NMOS inverters, pull-up load is constructed from a ____ mode transistor
  4. 8. Most basic element in building logic circuits
  5. 11. Different inverter designs will yield different overall area, ___ and power consumption