PLD's No Spaces

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Across
  1. 3. Test Data Out. In a JTAG port, the serial output data from a device.
  2. 7. A technique of entering CPLD design information by using a CAD (computer aided design) tool to draw a logic circuit as a schematic. The schematic can then be interpreted by design software to generate programming information for the CPLD.
  3. 8. Test Data In. In a JTAG port, the serial input data to a device.
  4. 14. Class of PLDs that contain an array of more complex logic cells that can be very flexibly interconnected to implement high-level logic circuits.
  5. 16. Test Clock. The JTAG signal that drives the JTAG downloading process from one state to the next.
  6. 17. A PLD with a few hundred logic gates and possibly a few programmable macro cells available.
  7. 18. Transferring design information from the computer running PLD design software to the actual PLD chip.
  8. 19. An industry standard form of text file indicating which fuses are blown and which are intact in a programmable logic device.
Down
  1. 1. Digital integrated circuit that can be programmed by the user to implement any digital logic function.
  2. 2. The process used by CPLD design software to interpret design information (such as a schematic or text file) and create required programming information for a CPLD.
  3. 4. The process of using software tools to describe the design requirements of a PLD. Design entry can be done by entering a schematic or a text file that describes the required digital function.
  4. 5. Joint Test Action Group. A standards body that developed the format for testing and programming devices while they are installed in a system.
  5. 6. An electronic circuit having many components, such as transistors, diodes, resistors, and capacitors, in a single package.
  6. 9. Assigning internal PLD circuitry, and input and output pins, to a PLD design.
  7. 10. A digital device consisting of several programmable sections with internal interconnections between the sections.
  8. 11. The specific PLD for which a digital design is intended.
  9. 12. A four-wire interface specified by the Joint Test Action Group (JTAG) used for loading test data or programming data into a PLD installed in a circuit.
  10. 13. Joint Electron Device Engineering Council.
  11. 15. Test Mode Select. The JTAG signal that controls the downloading of test or programming data.