Symmetric and Distributed Shared Memory Architectures, Cache coherence

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Across
  1. 1. Multiple simultaneous instruction streams operating on multiple data stream(4 Letters)
  2. 3. Time to access all the memory location will be same for all the core architecture (3 letters)
  3. 5. Communication wires are shared by the devices called (3 letters)
  4. 7. A collection of commodity systems connected by interconnection networks (7 Letters)
  5. 9. A processor that is able to process sequences of data with a single instruction (16 letters with 2 words)
  6. 11. the boss of CPU(11 letters with 2 words)
Down
  1. 2. data structure used in directory based cache coherence is (9 Letters)
  2. 4. the worker of CPU(3 Letters)
  3. 5. a number of simultaneous connection or connectivity in toroidal mesh interconnects. (14 letters with 2 words)
  4. 6. data is written in the cache and the corresponding main memory location at same time is called (12 letters, 2 words)
  5. 8. Language provide some of the mechanism of shared memory programs.
  6. 10. Applies the same instruction to multiple data items or it’s idle (4 Letters)