Verilog

3. The assignment a <= 1 is an example of this type (11)
5. In "always @(x,y,z) ..." x,y,z are part of this list (11)
6. An assignment of the form wire sum = a ^ b ^ c is of this type (10)
8. An assignment of the form reg sum; sum = a ^ b ^ c is of this type (10)
9. In "module adder #(?? N = 4)" what keyword must replace ?? (9)
10. The character # in Verilog is intended for introducing a (5)
12. What keyword can be prefixed to a series of if-else to prevent synthesizing priority encoder? (6)
13. In this type of state machine, the output logic is a function of only the state (5)
16. In this type of state machine, the output logic is a function of both primary inputs and state (5)
17. always @(*) is same as this in System Verilog (5,1,4)
19. If an always block contains a number of blocking statements, they will be executed ____ (12)
20. $display, $write, $sin etc. are examples of this (6,4)

1. If several initial blocks are placed one after another in a module, they will be executed ___ in simulation (12)
2. In "module ADDER (inbus in_x, inbus in_y, outbus out_x)" inbus and outbus are predefined as ___ (9)
4. If 4 flops have been used to build a state machine that has 11 states, then the state encoding is (6)
7. What clause, when added inside a case statement where only some of the conditions are checked, will prevent latches in synthesis? (7)
11. If you see initial statements in a Verilog module, it must be a (9)
14. If 11 flops have been used to build a state machine that has 11 states, then the state encoding is (6)
15. What kind of hardware description is "assign sum = a ^ b ^ c" an example of ? (8)
18. If you want each invocation of task to have its own set of local variables you must declare the task as (9)