Verilog HDL- Module 1

Edit Answers
1234567891011121314
Across
  1. 3. Does verilog allows mix & match of all 4 levels?
  2. 4. Integration level number of transistors <100
  3. 5. Which level abstraction is technology dependent
  4. 7. The process of creating objects from module
  5. 9. verilog HDL starts with a keyword
  6. 10. Cells which cannot be further divided
  7. 13. I am more flexible abstraction level
Down
  1. 1. verify the functionality of circuits
  2. 2. what is standardized as IEEE 1364?
  3. 6. At which description level design bugs to be fixed
  4. 8. How many basic types of digital design methodologies?
  5. 11. Verilog allows nested modules IS true/fALSE
  6. 12. Simulation block is also called as
  7. 14. More then 1,00,000 transistor which Integration?